Impact of Gate Leakage on the Performance of Analog Integrated Circuits - A Simulation Study

Direct tunneling current through the gate oxide is becoming a significant component of transistor leakage in deep sub-micron technology. This paper studies how gate leakage impacts the performance of analog CMOS ICs for the 90nm node. Results show that in DC referencing circuits such as current mirrors, a tradeoff exists between transistor width and mirrored reference current to improve accuracy. Further, sensitivity of differential amplifiers to gate leakage has been analyzed. Results also show that while errors due to threshold mismatch decrease with increase in device sizes, errors due to gate leakage correspondingly increase. Recommendations for bias, loading conditions and device sizes to combat these issues have been presented. Therefore investigations have to be done to develop immunity to gate leakage for various analog circuit blocks and topologies depending on device sizes and bias conditions and ignoring this effect leads to considerable error in estimation of circuit performance.